1. FIELD OF THE INVENTION
The present invention relates to an information processing apparatus and method using a central processing unit for fetching an instruction stored in a storage and executing the instruction, and a scheduling device for arranging instructions for information processing. In particular, the present invention relates to an information processing apparatus and method, and a scheduling device for performing a process which requires a relatively long time period.
2. DESCRIPTION OF THE RELATED ART
Information processing apparatuses such as microcomputers, microprocessors and the like have been proliferated and are used in various fields due to the recent development in electronic technologies. Specifically in recent years, the operating frequency of central processing units (CPUs) such as microcomputers, microprocessors and the like has been increased due to the size reduction of semiconductor devices and development in high-speed circuit technologies. Some CPUs operate at a frequency of as high as several hundred megahertz. The performance of the CPU is improved by the higher operating frequency, but the access rate from the CPU to an external memory for storing instruction codes to be executed and data is relatively slow, namely, several to several tens of times the operating frequency of the CPU. Since access to the external memory from the CPU which is made for performing an operation requires a relatively long time period, the performance of the information processing apparatus as a whole is not improved.
In addition to access to the external memory, operations which require a relatively long time period (e.g., mathematical operation) are performed by an information processing apparatus including a CPU which can operate at a relatively high speed. When performing such operations, the significant difference in process rate between inside and outside the CPU results in a lower information process efficiency.
Hereinafter, a structure of a conventional information processing apparatus and the operation thereof for accessing an external memory will be described.
FIG. 9 is a schematic view of a main part of a conventional information processing apparatus 800. As shown in FIG. 9, the information processing apparatus 800 includes a processor 810 and an external memory 850. The processor 810 and the external memory 850 are connected to each other via an external address bus 851 (851a and 851b) and an external data bus 852 (852a and 852b).
The processor 810 includes a central processing unit (hereinafter, referred to as a "CPU") 820, a bus control unit 830, and a ROM 840. The bus control unit 830 includes an address decoder 833, a control circuit 834, a memory access signal generation section 835, an address interface section 836 and a data interface section 837. The CPU 820 and the bus control unit 830 are connected to each other via an address bus 821 for sending addresses and a data bus 822 for transferring data. From the ROM 840, programs and instructions are sent to the CPU 820 via an instruction bus 841.
As shown in FIG. 9, an address which is output from the CPU 820 is supplied to the decoder 833 and the address interface section 836 via the address bus 821. The data bus 822 is connected to the data interface section 837. The address interface section 836 is connected to the external address bus 851 via the address bus 851a, and the data interface section 837 is connected to the external data bus 852 via the data bus 852a.
The CPU 820 outputs a read request signal 901 to the bus control unit 830 to request a read operation of data, and outputs a write request signal 902 to the bus control unit 830 to request a write operation of data. The read request signal 901 and the write request signal 902 are input to the control circuit 834 of the bus control unit 830. A decode address 903 is supplied to the address decoder 833 via a part of the address bus 821. The address decoder 833 decodes the decode address 903 and outputs the result to the control circuit 834 as a device identification signal 904. The device identification signal 904 indicates the target of access; e.g., whether the external memory 850 should be accessed from the CPU 820, or which device in the processor 810 should be accessed from the CPU 820.
The control circuit 834 outputs an external access start signal 905, an address control signal 906 for controlling the address interface section 836, and a data control signal 907 for controlling the data interface section 837 based on the device identification signal 904, the read request signal 901 and the write request signal 902. The control circuit 834 also outputs a response signal 908 in response to the read request signal 901 and the write request signal 902 from the CPU 820. The memory access signal generation section 835 outputs a memory access signal 909 for accessing the external memory 850 based on the external access start signal 905 supplied from the control circuit 834. The external memory 850 receives the memory access signal 909, and when the access is completed, the external memory 850 outputs an external response signal 910 for notifying the processor 810 of the completion of the access operation. The external response signal 910 is supplied to the control circuit 834 of the bus control unit 830.
The conventional information processing apparatus 800 having the above-described structure operates, for example, in the following manner. First, an example of a program stored in the ROM 840 including instructions which are executed solely by the CPU 820 and instructions which are executed cooperatively by the CPU 820 and the bus control unit 830 will be described. Regarding each of the following instructions, the operation indicated by the instruction is described in the parentheses. For example, instructions 11 through 13 indicate a process for accessing the external memory 850 and using data obtained as a result of the access operation. Instructions 14 through. 17 indicate a process performed solely by the CPU 820. The numerical figures, calculations, and the like used in the following instructions are simply illustrative. Other numerical figures and calculations may also be used.
Instruction 11: MOV @mem.sub.-- loc1, D0
(Data is read from address mem.sub.-- loc1 of the external memory 850 and stored in register D0 in the CPU 820.)
Instruction 12: ADD #10, D0
(The content in register D0 in the CPU 820 and 10 are added together, and the result is stored again in register D0.)
Instruction 13: MOV @mem.sub.-- loc2, D2
(Data is read from address mem.sub.-- loc2 of the external memory 850 and stored in register D2 in the CPU 820.)
Instruction 14: MUL D0, D2
(The content in register D2 in the CPU 820 is multiplied by the content in register D0, and the result is stored again in register D2.)
Instruction 15: ADD #1, D1
(The content in register D1 in the CPU 820 and 1 are added together, and the result is stored again in register D1.)
Instruction 16: ADD #4, A0
(The content in register A0 in the CPU 820 and 4 are added together, and the result is stored again in register A0.)
Instruction 17: ADD #4, A1
(The content in register A1 in the CPU 820 and 4 are added together, and the result is stored again in register A1.)
With reference to FIGS. 10A and 10B, the operation of the information processing apparatus 800 for running the above-described program will be described from cycles t1 through t13. FIG. 10A and 10B are operational timing diagrams of the information processing apparatus 800. Cycles t1 through t6 are shown in FIG. 10A, and cycles t7 through t13 are shown in FIG. 10B. In this example, the read time of the external memory 850, namely, the time period from the external memory 850 receives the memory access signal 909 and the address output to the external address bus 851 until the external memory 850 outputs the data to the external data bus 852 is 4 machine cycles. Data "data1" is pre-stored at address mem.sub.-- loc1 of the external memory 850, and data "data2" is pre-stored at address mem.sub.-- loc2 of the external memory 850.
When the instruction for reading the data from the external memory 850 (instruction 11 or 13) is processed by the CPU 820, the address of the data to be read (mem.sub.-- loc1 or mem.sub.-- loc2) is output to the external address bus 851 via the address bus 821 and the address interface section 836 (cycle t1 or t6). However, the read time of the external memory 850 is 4 cycles, which is longer than a time unit of the CPU 820 (1 machine cycle). Accordingly, until the data output from the external memory 850 (data1 or data2) reaches the data bus 822 via the external data bus 852 and the data interface section 837 (until cycle t4 or t9), the CPU 820 cannot perform the subsequent processes. In other words, the CPU 820 is put into a wait state before executing the subsequent instructions until the read operation of the data from the external memory is completed. Also in the case of performing a mathematical operation which also requires a relatively long process time, the CPU 820 is put into a wait state before executing the subsequent instructions until the mathematical operation is completed.
In such a conventional information processing apparatus, the CPU is put into a wait state before executing the subsequent instructions due, for example, to read operations of the data from the external memory or mathematical operations both of which require a relatively long time period. Thus, it is demanded to minimize the penalty (e.g., reduction in the process efficiency) due to the wait time.
In order to shorten the apparent access time to the external memory, for example, it has been proposed to mount a cache memory for buffering the data which has been once read or a prefetch buffer for prefetching the data from the external memory in a microcomputer or microprocessor.
However, mounting a cache memory or a prefetch buffer in a microcomputer or microprocessor significantly increases the size of hardware although reducing the penalty. Moreover, the access time to the cache memory and the time required for the complicated control reduces the operating frequency.